The present invention relates to a method and architecture for power-on-reset generally and, more particularly, to a method and architecture for an oscillator based power-on-reset.
Conventional power-on-reset circuits use large on-chip resistor dividers to establish trip points with respect to the transistor threshold. These resistors add complexity and require a large area on the chip. Due to the large charge/discharge time associated with the resistor dividers, the time it takes for the power on reset circuit to reset during a drop in voltage (brown-out performance) can be slower than required. FIG. 1 illustrates an example of such a conventional circuit.
The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first signal comprising a series of one or more pulses. The second circuit may be configured to generate a second signal in response to the first signal. The second signal may be configured to control the reset of an external device. In one example, the present invention may be implemented as a power on reset circuit.
The object features and advantages of the present invention include providing a method and/or architecture for a power on reset circuit that may (i) be implemented with any relaxation oscillator, (ii) reduce the overall circuit complexity, (iii) reduce the overall circuit size, (iv) provide guaranteed stability, (v) improve a brown out detection, (vi) be insensitive to power supply ramp, and/or (vii) be insensitive to process variation (C and R does not vary much).